The present invention relates to semiconductor design technologies; and, more particularly, to a sense amplifier for use in a semiconductor memory device. More specifically, the present invention is directed to a sense amplifier enable signal generator for controlling the sense amplifier of the semiconductor memory device.
Generally, a memory device such as DRAM (Dynamic Random Access Memory) is provided with a bit line sense amplifier for amplifying a fine potential difference of a pair of bit lines for read or refresh driving.
For reference, the procedure of outputting data stored in cells through a read operation in DRAM will be described around the operation of such a bit line sense amplifier as follows.
First, when an RAS signal /RAS among external commands for operating DRAM is activated, an input address signal is applied to a row address buffer which performs a row decoding operation wherein the row address signal is decoded to select a word line to which a cell where a data to be outputted is stored belongs.
In this manner, when a word line is selected and at the same time a data of a plurality of cells coupled to the selected word line is carried on plural pairs of bit lines BL and BLB, the bit line sense amplifier is driven to amplify the data of the plural pairs of bit lines BL and BLB.
Next, any one of the plural pairs of bit lines BL and BLB is selected by a column address by a column decoder and the data of the selected pair of bit lines BL and BLB is outputted through a segment input/output line SIO, a local input/output line LIO and a global input/output line GIO.
Meanwhile, a sense amplifier enable signal used herein denotes a signal for determining when a sense amplifier amplifies the data carried on the pair of bit lines BL and BLB by the selected word line in such a read operation of DRAM. Typically, such a sense amplifier enable signal is generated by the following method.
FIG. 1 is a circuit diagram showing a configuration of a bit line sense amplifier array and a memory cell array including a sense amplifier enable signal generator of DRAM according to the prior art.
Referring to FIG. 1, the memory cell array 140 includes a plurality of word lines WL0, WL1, WL2 and WL3, and a sub word driver for driving the plurality of word lines WL0, WL1, WL2 and WL3.
Although one cell is shown to be configured for one word line in FIG. 1, it is merely for simplicity of drawing and a plurality of cells are generally arranged for one word line.
Further, even if the memory cell array 140 is configured only above the bit line sense amplifier array in the drawing, it is usually provided above and below the bit line sense amplifier array.
Typically, therefore, the memory cell array above the bit line sense amplifier array is called an ‘upper memory cell array’ and the memory cell array below the bit line sense amplifier array is called a ‘lower memory cell array’.
The bit line sense amplifier array is provided with a bit line sense amplifier 130, an upper bit line separator 150 and a lower bit line separator 180, a bit line equalization/precharge part 160, a column selector 170, a bit line sense amplifier power line driver 120 and a driver controller 110, (regardless of the sense amplifier enable signal generator 100.)
The driver controller 110 drives a pull-down power line SB and a pull-up power line RTO for controlling the operation of the power line driver 120 with a predetermined voltage level in response to a sense amplifier enable signal SAE outputted from the sense amplifier enable signal generator 100.
The upper bit line separator 150 is to separate/connect the upper memory cell array from/to the bit line sense amplifier 130 in response to an upper separation signal BISH, and the lower bit line separator 180 is to separate/connect the lower memory cell array from/to the bit line sense amplifier 130 in response to a lower separation signal BISH.
The bit line sense amplifier 130 senses a voltage difference (having a fine voltage difference by charge sharing) of a pair of bit lines BL and BLB when the sense amplifier enable signal SAE is activated so that the pull-down power line SB and the pull-up power line RTO are driven to a predetermined voltage level by the driver controller 110, and then amplifies one of the bit lines to a ground voltage VSS and the other to a core voltage VCORE.
The bit line equalization/precharge part 160 serves to precharge the pair of bit lines BL and BLB to a bit line precharge voltage VBLP (conventionally, VCORE/2) in response to a bit line equalization signal BLEQ, after completing the sensing/amplification and restoration procedure for the bit lines.
The column selector 170 transfers the data of the pair of bit lines BL and BLB sensed/amplified by the bit line sense amplifier 130 to segment data buses SIO and SIOB in response to a column selection signal YI when a read command is applied thereto.
Meanwhile, the sense amplifier enable signal generator 100 is provided with a default delay circuit 102 and a sense amplifier enable signal output circuit 104.
The default delay circuit 102 delays an active command signal ACT activated in response to an RAS signal /RAS by a predetermined sensing delay to output a sense amplifier activation control signal SAEA.
The sense amplifier enable signal output circuit 104 activates the sense amplifier enable signal SAE in response to the sense amplifier activation control signal SAEA and inactivates the same in response to a precharge command signal PCG.
FIG. 2 is a timing diagram illustrating the sensing and amplifying procedure of the bit line sense amplifier including the sense amplifier enable signal generator shown in FIG. 1.
Referring to FIG. 2, the bit line sense amplifier 130 senses and amplifies the data of the pair of bit lines BL and BLB through the following steps.
First of all, a word line WL to which a cell where a data to be outputted is stored belongs is activated in response to the active command signal ACT activated by the row decoding operation set forth above.
When the word line Wl is activated, a fine voltage difference occurs between the pair of bit lines BL and BLB due to a charge sharing phenomenon in which the data of the cell belonging to the word line is transferred to the pair of bit lines BL and BLB.
Thereafter, when the sense amplifier enable signal SAE is activated in response to the signal SAEA that is obtained by delaying the active command signal ACT used in activating the word line WL by a predetermined sensing delay, the bit line sense amplifier 130 senses a fine voltage difference of the pair of bit lines BL and BLB and amplifies one of them to the ground voltage VSS and the other to the core voltage VCORE.
By the way, the sense amplifier enable signal generator 100 mentioned above delays the active command signal ACT used in activating the word line WL by a predetermined sensing delay which is a fixed delay value regardless of the input/output bandwidth of DRAM, and employs it in activating the sense amplifier enable signal SAE.
In case the sense amplifier enable signal SAE is activated by using the fixed delay value as above, some problems may be generated as follows.
FIG. 3 is a diagram showing word lines of banks activated correspondingly to an input/output bandwidth.
Referring to FIG. 3, the number of word lines of banks activated correspondingly to an input/output bandwidth can be seen.
First, an IO<0:7> line is connected to a bank BANK0_0, an IO<8:15> line is connected to a bank BANK0_1, an IO<16:24> line is connected to a bank BANK0_2, and an IO<25:32> line is connected to a bank BANK0_3.
That is, in the input/output bandwidth of X8, one of IO<0:7>, IO<8:15>, IO<16:24>, and IO<25:32> lines is enabled in one input/output operation and only one of BANK0_0, BANK0_1, BANK0_2, and BANK0_3 regions is selected, and thus, only one word line is activated in one input/output operation.
Further, in the input/output bandwidth of X16, two of IO<0:7>, IO<8:15>, IO<16:24>, and IO<25:32> lines are enabled in one input/output operation and two of BANK0_0, BANK0_1, BANK0_2, and BANK0_3 regions are selected, and thus, two word lines are activated in one input/output operation.
Also, in the input/output bandwidth of X32, all of IO<0:7>, IO<8:15>, IO<16:24>, and IO<25:32> lines are enabled in one input/output operation and all of BANK0_0, BANK0_1, BANK0_2 and BANK0_3 regions are selected, and thus, four word lines are activated in one input/output operation.
Therefore, it can be seen that the number of word lines activated in one input/output operation increases as the input/output bandwidth increases.
By the way, if the number of word lines activated in one input/output operation increases, the amount of current consumed by DRAM in one input/output operation increases, which causes a phenomenon in which a voltage level used therein becomes lower than a desired level.
Thus, the bit line sense amplifier 130 may involve the following problems by the aforementioned phenomenon that also occurs in the sense amplifier enable signal generator 100 that is one of voltages used in the DRAM.
FIG. 4A is a timing diagram illustrating one example of defects which may happen due to malfunctioning of the sense amplifier enable signal generator of the semiconductor memory device according to the prior art in the sensing and amplifying procedure of the bit line sense amplifier shown in FIG. 1.
Referring to FIG. 4A, when a predetermined sensing delay of the sense amplifier enable signal generator 100 is fixed so that the bit line sense amplifier 130 is optimized in the input/output bandwidth of X8 and operated, a solid line represents an operation waveform of the bit line sense amplifier 130 that operates in the input/output bandwidth of X8, and a dotted line denotes an operation waveform of the bit line sense amplifier 130 that operates in the input/output bandwidth of X32.
With reference to the solid line, the bit line sense amplifier 130 that operates in the input/output bandwidth of X8 normally amplifies the data of the pair of bit lines BL and BLB without any problem, like that shown in FIG. 2.
However, with reference to the dotted line, the bit line sense amplifier 130 that operates in the input/output bandwidth of X32 may cause a problem that a fine voltage level difference that has to be occurred between the pair of bit lines BL and BLB becomes less than a voltage level difference that can be sensed by the bit line sense amplifier 130 because of a late occurrence of a charge sharing phenomenon in which the data of cell belonging to the word line is transferred to the pair of bit lines BL and BLB due to a gentle slope of the word line WT activated in response to the active command signal ACT.
As such, if the fine voltage level difference between the pair of bit lines BL and BLB becomes less than the voltage level difference that can be sensed by the bit line sense amplifier 130, there may occur a defect that the bit line sense amplifier 130 inversely senses and amplifies the data as shown.
FIG. 4B is a timing diagram illustrating another example of defects which may happen due to malfunctioning of the sense amplifier enable signal generator of the semiconductor memory device according to the prior art in the sensing and amplifying procedure of the bit line sense amplifier shown in FIG. 1.
Referring to FIG. 4B, when the predetermined sensing delay of the sense amplifier enable signal generator 100 is fixed so that the bit line sense amplifier 130 is optimized in the input/output bandwidth of X32 and operated, a solid line represents an operation waveform of the bit line sense amplifier 130 that operates in the input/output bandwidth of X32, and a dotted line denotes an operation waveform of the bit line sense amplifier 130 that operates in the input/output bandwidth of X8.
With reference to the solid line, the bit line sense amplifier 130 that operates in the input/output bandwidth of X32 normally amplifies the data of the pair of bit lines BL and BLB without any problem, like that shown in FIG. 2.
However, with reference to the dotted line, the bit line sense amplifier 130 that operates in the input/output bandwidth of X8 may raise a problem that an operation speed of the entire DRAM including the bit line sense amplifier 130 becomes slow because the sense amplifier enable signal SAE is activated to operate the bit line sense amplifier 130 at a certain time after an occurrence of a charge sharing phenomenon in which the data of cell belonging to the word line is transferred to the pair of bit lines BL and BLB due to a sharp slope of the word line WL activated in response to the active command signal ACT.
In addition, in order to solve the aforementioned problem caused by variation of a target input/output bandwidth of DRAM in its design, the conventional method modifies an inner circuit configuration of DRAM, but this increases costs and takes time for development.